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Intel® Xeon® Processor 7400 Series Datasheet 37

Electrical Specifications

2.13 Front Side Bus AC Specifications

The processor FSB timings specified in this section are defined at the

processor core (pads). Therefore, proper simulation of the FSB is the only

means to verify proper timing and signal quality.

See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through

Table 2-24 list the AC specifications associated with the processor FSB.

All AGTL+ timings are referenced to GTLREF_DATA_MID, GTLREF_DATA_END,

GTLREF_ADD_MID, and GTLREF_ADD_END for both ‘0’ and ‘1’ logic levels unless

otherwise specified.

The timings specified in this section should be used in conjunction with the processor

signal integrity models provided by Intel. AGTL+ layout guidelines are also available in

the appropriate platform design guidelines.

Note: Care should be taken to read all notes associated with a particular timing parameter.

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is

determined during initialization as described in Section 2.3. Table 2-1 includes core frequency to FSB

multipliers.

3. The period specified here is the average period. A given period may vary from this specification as

governed by the period stability specification (T2).

4. For the clock jitter specification, refer to the CK410B Clock Synthesize/Driver Design Guidelines.

5. In this context, period stability is defined as the worst case timing difference between successive crossover

voltages. In other words, the largest absolute difference between adjacent clock periods must be less than

the period stability.

6. Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing.

7. Measured from -200 mV to +200 mV. The signal must be monotonic through the measurement region for

rise and fall time. The 400 mV measurement window is centered on the differential zero. See Figure 2-11.

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Not 100% tested. Specified by design characterization.

3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V

CROSS

) of the

BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at nominal

GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor

(pads).

Table 2-19. Front Side Bus Differential Clock AC Specifications

T# Parameter Min Typ Max Unit Figure Notes

FSB Clock Frequency 265.247 266.666 266.745 MHz 2

T1: BCLK[1:0] Period 3.7489 3.7500 3.7700 ns 2-9 3

T2: BCLK[1:0] Period Stability 150 ps 4, 5

T3: BCLK[1:0] Rise Time 700 ps 6

T4: BCLK[1:0] Fall Time 700 ps 6

Differential Rising and Falling Edge

Rates

0.6 4 V/ns 7

Table 2-20. Front Side Bus Common Clock AC Specifications

T# Parameter Min Max Unit Figure Notes

1, 2, 3

T10: Common Clock Output Valid Delay 0.22 1.10 ns 2-12 4

T11: Common Clock Input Setup Time 0.650 N/A ns 2-12 5

T12: Common Clock Input Hold Time 0.150 N/A ns 2-12 5

T13: RESET# Pulse Width 1 10 ms 2-20 6, 7, 8

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 135 136

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